History

How it Works

How does FlexHDR go from source code to FPGA design?

Templated HDL (THDL)

FlexHDR comes with two kinds of sources: templated and non-templated sources. The non-templated sources are regular vhdl and verilog files. These files are used directly in the FPGA project. The templated sources do not get used directly in the FPGA project. Rather, the templated sources generate a verilog or vhdl source at runtime. The generated source file name and module/entity name is a 1 to 1 function of the input parameters, to avoid name space collisions in the file system or in the FPGA project. All of this generation magic is taken care of by FlexHDR when the top level file is generated.

The reason for templated sources is that vhdl and verilog can be very limiting: the number of ports and parameters is static, the data types for ports and parameters is static. Take for example, the adder. We would like to see an adder block in FlexHDR that can add signed, unsigned, sfixed, and ufixed numbers. Also, we may like the adder to have 2, 3, or maybe 4 input ports. However, to do this in vhdl would require one entity and architecture for each combination of data type and number of ports. The solution is to use a template that will generate the type of adder required.

Templated sources also allow the templates to do complicated pre-processing tasks, and then hard code the result into the generated source. This is particularly valuable for verilog which has no preprocessing capabilities. For example, the template could use trigonometric functions and complex math to calculate filter coefficients from a set of parameters. The resulting coefficients would get coded into the generated source. Doing this calculation would have been difficult or maybe impossible in the hardware description language itself.

Block Wrappers

Block wrappers are xml data files that contain all of the information about a HDL source that is needed by the GUI: parameters, ports, data types, etc... Some block wrappers are automatically generated from the HDL source files. For the automatically generated block wrappers, special comments may be added to the HDL source to pass additional data into the block wrapper, see SpecialComments. More complex scenarios require that block wrappers are manually written. Examples include THDL sources and custom block wrappers that represent more than one HDL source file.

HDL Sources - Properties File

The properties file, located in each HDL directory, associates multiple key/value parameters with a HDL or THDL source. These properties are:

  • *library: * The name of the vhdl library. All blocks in a given package must also be in the same library. (vhdl only)
  • *package: * The name of the vhdl package. Should be provided regardless of the gen_package setting. (vhdl only)
  • *view: * The Xilinx view setting: view_any, view_syn, or view_sim (All, Implementation, Simulation).
  • *wrap: * An on/off property. Use the lexer to automatically create a block wrapper from the HDL source file (leave undefined for off).
  • *package_template: * An on/off property. This source will be identified as a package template (leave undefined for off). (vhdl only)

The properties files, called sources.csv, is a comma-separated-value file. Each line of the file contains 3 items: the relative path to the source, the key, and the value.

sources.csv

my_block.vhd, library, flexhdr
my_block.vhd, package, blocks

ISE Simulator

FlexHDR uses ISE's built-in simulator to simulate a top block module. Simulation is a 3 step process. First, FlexHDR generates all dependent sources and creates a .prj file that lists all of the sources. Second, ISE's fuse compiler is invoked with the .prj file as an argument. The fuse compiler calls the vhpcomp (vhdl) and vlogcomp (verilog) compilers on the sources and produces a simulation executable. And finally, the simulation executable is run, and outputs a vcd file. The .vcd file can be used to create wave traces and list plots. Future development will enable the FlexHDR gui to configure the wave traces and list plots to be automatically displayed after simulation.

Simulations can be controlled by configuring the clock simulation block in the top level module. Also, custom test benches can be written in vhdl or verilog and instantiated in the top level module.

ISE Synthesizer

FlexHDR uses the Xilinx TCL shell (xtclsh) to perform all of the synthesis processes (which can be found in the left panel of the ISE gui). FlexHDR generates a .tcl script that creates an ISE project, adds sources, sets properties, and finally, runs a process such as "Check Syntax" or "Generate Programming File". This .tcl script is passed to the xtclsh to be executed.